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INI File | 2002-05-24 | 4.4 KB | 99 lines |
- [-COMMENT-:GLOBAL]
- # VHDL-93 LANGUAGE KEYWORD FILE FOR CRIMSON EDITOR
- # Complete rewrite by Robert Ingham, 2002-04-09 et seq.
- # 2002-04-17: 'out' 'inout' only occur inside port_interface_lists;
-
- [KEYWORDS0:GLOBAL]
- # reserved words, except operators
- access after alias all architecture array assert attribute
- begin block body buffer bus case component configuration constant
- disconnect downto else elsif end entity exit
- file for function generate generic group guarded
- if impure in inertial inout is
- label library linkage literal loop
- map new next null of on open others out
- package port postponed procedure process pure
- range record register reject report return
- select severity shared signal subtype
- then to transport type
- unaffected units until use
- variable wait when while with
-
- [KEYWORDS1:GLOBAL]
- # reserved words: operators
- abs and mod nand nor not or rem rol ror sla sll sra srl xnor xor
-
- [KEYWORDS2:RANGE1]
-
- [KEYWORDS3:GLOBAL]
- # standard (predefined) attributes
- left right low high ascending image value pos val succ pred leftof rightof base range reverse_range length
- delayed stable quiet transaction event active last_event last_active last_value driving driving_value
- simple_name path_name instance_name
-
- [KEYWORDS4:GLOBAL]
- # names of standard libraries and packages
- std ieee work
- standard textio
- std_logic_1164 std_logic_arith std_logic_misc std_logic_signed std_logic_textio std_logic_unsigned numeric_bit numeric_std math_complex math_real vital_primitives vital_timing
-
- [KEYWORDS5:GLOBAL]
- # function and procedure names defined in standard packages
- now
- readline read writeline write endfile
- resolved to_bit to_bitvector to_stdulogic to_stdlogicvector to_stdulogicvector to_x01 to_x01z to_UX01 rising_edge falling_edge is_x
- shift_left shift_right rotate_left rotate_right resize to_integer to_unsigned to_signed std_match to_01
-
- [KEYWORDS6:GLOBAL]
- # types and subtypes defined in standard packages
- boolean bit character severity_level integer real time delay_length natural positive string bit_vector file_open_kind file_open_status
- line text side width
- std_ulogic std_ulogic_vector std_logic std_logic_vector X01 X01Z UX01 UX01Z
- unsigned signed
-
- [KEYWORDS7:GLOBAL]
- # enumeration type values defined in standard packages
- false true note warning error failure fs ps ns us ms sec min hr read_mode write_mode append_mode open_ok status_error name_error mode_error
- # next line are (incomplete) values for CHARACTER type
- nul soh stx etx eot enq ack bel bs ht lf vt ff cr so si dle dc1 dc2 dc3 dc4 nak syn etb can em sub esc fsp gsp rsp usp
- # right left
- # PROBLEM: 'left' also an attribute
-
- [KEYWORDS8:GLOBAL]
- # LPM library, package, component (= module) names
- LPM LPM_COMPONENTS
- LPM_CONSTANT LPM_INV LPM_AND LPM_OR LPM_XOR LPM_BUSTRI LPM_MUX LPM_DECODE LPM_CLSHIFT LPM_ADD_SUB LPM_COMPARE LPM_MULT LPM_DIVIDE LPM_ABS LPM_COUNTER LPM_LATCH LPM_FF LPM_SHIFTREG LPM_RAM_DQ LPM_RAM_DP LPM_RAM_IO LPM_ROM LPM_FIFO LPM_FIFO_DC
- LPM_TTABLE LPM_FSM LPM_INPAD LPM_OUTPAD LPM_BIPAD
- # generics for LPM
- LPM_WIDTH LPM_CVALUE LPM_STRENGTH LPM_SIZE LPM_WIDTHS LPM_PIPELINE LPM_DECODES LPM_WIDTHDIST LPM_SHIFTTYPE
- LPM_DIRECTION LPM_REPRESENTATION LPM_WIDTHA LPM_WIDTHB LPM_WIDTHS LPM_WIDTHP LPM_WIDTHN LPM_WIDTHD
- LPM_NREPRESENTATION LPM_DREPRESENTATION LPM_MODULUS LPM_DIRECTION LPM_AVALUE LPM_SVALUE LPM_PVALUE LPM_FFTYPE
- LPM_WIDTHAD LPM_NUMWORDS LPM_INDATA LPM_OUTDATA LPM_ADDRESS_CONTROL LPM_RDADDRESS_CONTROL LPM_WRADDRESS_CONTROL
- LPM_FILE LPM_SHOWAHEAD LPM_WIDTHU LPM_WIDTHIN LPM_WIDTHOUT LPM_TRUTHTYPE LPM_TYPE LPM_HINT
-
- [KEYWORDS9:GLOBAL]
- # Verilog keywords - for maximum portability, these are best avoided
- # also includes some words that are also VHDL keywords, but doesn't matter in this context
- always and assign attribute
- begin bufif0 bufif1
- case casex casez cmos
- deassign default defparam disable
- edge else end endattribute endcase endfunction endmodule endprimitive endspecify endtable endtask event
- for force forever fork function
- highz0 highz1
- if ifnone initial inout input integer
- join
- large
- macromodule medium module
- nand negedge nmos nor not notif0 notif1
- or output
- parameter pmos posedge primitive pull0 pull1 pulldown pullup
- real realtime reg release remos repeat rnmos rpmos rtran rtranif0 rtranif1
- scalared signed small specify specparam strength strong0 strong1 supply0 supply1
- table task time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg
- unsigned
- vectored
- wait wand weak0 weak1 while wire wor
- xnor xor
-
-